1. Field of the Invention
This invention relates to the field of circuits.
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2. Background Art
Computer systems are comprised of components that consist of millions of integrated circuits. Computer system performance can sometimes be greatly improved by improving the performance of individual circuits. One type of circuit in a computer system is referred to as a two-way data port. Current data port circuits are complex and have a relatively large number of transistors. It is desired to reduce the number of devices in a data port to improve the performance of data port circuits.
Data Port Operation
A data port is a circuit that has two inputs (A and B) and produces two outputs (D and E). The data port can be configured to have the data on the A input passed to the D output, with the data on the B input passed to the E output, or the data port can be configured to have the data on the A input passed to the E output, with the data on the B input passed to the D output. The operation of the data port is controlled by an input control signal C that determines the input/output configuration of the data port.
The logical configuration of a two way data port is illustrated in FIG. 1. Referring to FIG. 1, a two way data port 100 is shown with A and B inputs 101 and 102 respectively. The D and E are shown as outputs 104 and 105 respectively. The control signal C is shown as signal 103. In the embodiment shown, when signal C is asserted, the A and B inputs are routed to outputs D and E respectively. When the inverse of signal C is asserted, the A and B inputs are routed to outputs E and D respectively.
Prior Art Circuit Implementations
First Prior Art Embodimentxe2x80x94FIG. 2 is an example of a first prior art implementation of the two way data port of FIG. 1. Input signal A is coupled through inverter 202 to the input of standard cell circuit 203.1 and to the input of standard cell circuit 203.4. Input B is coupled through inverter 206 to the input of standard cell 203.2 and to the input of standard cell 203.3.
The outputs of standard cells 203.1 and 203.2 are coupled to D output 204. The outputs of standard cells 203.3 and 203.4 are coupled to E output 205. Standard cells 203.1 and 203.3 are enabled by signal CI 210, and standard cells 203.2 and 203.4 are controlled by signal CB 211. These signals are created when C input 207 is provided through inverter 208 to yield signal CB 211 and again through inverter 209 to yield signal CI 210. When C input 207 is high, signal CI 210 is high and signal CB 211 is low. This enables standard cells 203.1 and 203.3 while disabling 203.2 and 203.4. As a result, input A is coupled to output D and input B is coupled to output E.
When C input 207 is low, signal CI 210 is low and signal CB 211 is high. This enables standard cells 203.2 and 203.4, disabling 203.1 and 203.3. As a result, input A is now coupled to output E and input B is coupled to output D.
Each standard cell 203.1 through 203.4 of FIG. 2 is implemented with the circuit of FIG. 3. FIG. 3 comprises PMOS transistors M1-M7 and NMOS transistors M8-M14. The sources of PMOS transistors M1, M2 and M4-M7 are coupled to the upper voltage reference node. The sources of NMOS transistors M8, and M10-M14 are coupled to the lower voltage reference node. Input E is applied to the gates of PMOS transistors M1 and M5 and NMOS transistors M9 and M11. Input A is applied to the gates of PMOS transistor M4 and NMOS transistor M14. Output node Axe2x80x2 (Y) is formed by the coupled drains of PMOS transistor M7 and NMOS transistor M8. The drains of PMOS transistor M1 and NMOS transistor M11 are coupled to the gates of PMOS transistor M2 and NMOS transistor M12 to form node 4. The drains of PMOS transistor M4 and NMOS transistor M14 are coupled to the gates of PMOS transistors M3, M6, M13 and NMOS transistor M10 to form node 5. The drain of PMOS transistor M2 is coupled to the source of PMOS transistor M3 to form node 13, and the drains of PMOS transistor M3 and NMOS transistor M12 are coupled to the gate of NMOS transistor M8 and the drain of NMOS transistor M13 to form node 2. The drains of PMOS transistors M5 and M6 and NMOS transistor M9 are coupled to the gate of PMOS transistor M7 to form node 6. The source of NMOS transistor M9 is coupled to the drain of NMOS transistor M10 to form node 12.
A disadvantage of the circuit of FIG. 3 is that each standard cell uses 14 transistors. With four cells in the data port, 56 transistors are required for each data port. The cell is a tristate circuit and is inherently a poor driver. It uses larger area, more stages of delays, higher input capacitance, and is vulnerable to CB/CI skew induced transient current contentions.
Second Prior Art Embodimentxe2x80x94FIG. 4 illustrates a second prior art two way data port embodiment. The A input is coupled through inverter 402 to produce signal 405 coupled to the first input of standard cell 403.1 and to the second input of standard cell 403.2. The B input is coupled through inverter 404 to produce signal 406 coupled to the first input of cell 403.2 and to the second input of cell 403.1. Signal CI selects the first input of cells 403.1 and 403.2, while signal CB selects the second input of cells 403.1 and 403.2. The output of cell 403.1 is D output 407 and the output of cell 403.2 is E output 408.
When signal CI is enabled, the first input of cells 403.1 and 403.2 is selected so that the A input is coupled to the D output 407 and the B input is coupled to the E output 408. When signal CB is enabled, the second input of cells 403.1 and 403.2 is enabled so that the A input is coupled to the E output 408 and the B input is coupled to the D output 407.
Each of cells 403.1 and 403.2 is comprised of the circuit of FIG. 5. FIG. 5 comprises PMOS transistors M1-M4 and NMOS transistors M5-M8. The sources of PMOS transistors M1 and M2 are coupled to the upper voltage reference node. The drains of PMOS transistors M1 and M2 are coupled to the sources of PMOS transistors M3 and M4 to form node 7. The drains of PMOS transistors M3 and M4 are coupled to the drains of NMOS transistors M6 and M7 to form output node Y. The sources of NMOS transistors M6 and M7 are coupled to the drains of transistors M5 and M8, respectively, and the sources of transistors M5 and M8 are coupled to the lower voltage reference node. Input A is applied to the gates of transistors M3 and M7, input B is applied to the gates of transistors M4 and M8, input C is applied to the gate of transistors M2 and M6, and input D is applied to the gates of transistors of M1 and M5.
A disadvantage of the circuit of FIG. 5 is the number of transistors. With two cells required, a total of 16 transistors is required for the data port. Also, the circuit is a poor driver. It involves two NTx or PTx for tf or tr switching. It also has double input gate load to the previous stage.
The present invention provides a best circuit configuration for data port solutions. One embodiment uses a pair of transmission gates as bridges to realize 2xc3x972xc3x97D (Mxc3x97Nxc3x97D) logic switching in high speed (on the order of 5.0 TBPS) data switch ports. The simplicity of the circuit guarantees the physical closeness of the internal switching nodes D and E to their respective drivers. It also means least capacitance for those nodes. This circuit technique insures a high density, high speed, low power solution for any data port switching. The technique benefits a wide range of product applications ranging from high speed high bandwidth router to low power portable computing hardware.